1. Field of the Invention
The present invention relates to a pass transistor circuits, which includes a plurality of pass transistor sections. More particularly, the present invention relates to a pass transistor circuit produced by a CMOSFET (Complementary Metal-Oxide-Semiconductor Field-Effect Transistor) process utilizing a TFT (Thin Film Transistor) technique.
2. Description of the Related Art
Conventionally, in order to reduce the number of transistors used, a pass transistor circuit is implemented with pass logic sections (pass gates) each formed of either an n-type (n-channel) MOSFET or a p-type (p-channel) MOSFET.
FIGS. 5 and 6 illustrate such a conventional pass transistor circuit. As illustrated in the figures, the pass gate section of the pass transistor circuit includes four transistors Tr1 to Tr4, which are all n-type MOSFETs.
FIG. 7 illustrates another conventional pass transistor circuit. This pass transistor circuit is called a "CVSL (Cascode Voltage Swing Logic)" circuit developed by IBM corporation, where the pass gate sections of the pass transistor circuit are each formed only of an n-type MOSFET.
FIG. 8 illustrates still another conventional pass transistor circuit. This pass transistor circuit is called a "DPL (Double Pass-transistor Logic" developed by Hitachi Ltd, where the pass gate sections of the pass transistor circuit are each formed only of an n-type MOSFET.
The pass transistor circuit diagrams illustrated in FIGS. 5 to 8 are from "White paper on low power consumption LSIs", Nikkei Business Publications Inc.
Other conventional pass transistor circuits include those described in Japanese Laid-open Publication Nos. 8-321770 and 9-93118.
In the pass transistor circuit described in Japanese Laid-open Publication No. 8-321770, the pass gate section is formed only of either an n-type transistor or a p-type transistor.
The pass transistor circuit employs an output-latch-type circuit configuration, in which the output is fully swung, but the pass gate section is again formed only of a single transistor.
As described above, in the conventional pass transistor circuit, the pass gate section is formed only of either an n-type transistor or a p-type transistor.
Referring to FIGS. 6 and 9, a problem associated with such a conventional pass transistor circuit, where the pass gate section is formed only of an n-type MOSFET, will be described. FIG. 9 is a layout diagram illustrating a structure corresponding to that illustrated in FIGS. 5 and 6, with the pass transistor circuit sections being replaced by transistor circuits.
Consider a case where input signals A and B to the pass gate sections are each at a high level, and the n-type transistors Tr2 and Tr4 are both turned ON. When an input signal C is at a low level, an inverted signal C bar (inverted from the signal C) is first transmitted to a node N#1.
However, since the transistors Tr2 and Tr4 are both n-type MOSFETs, the high level signal which equals V.sub.DD, the positive power supply voltage) is not transmitted therethrough. Therefore, the node N#1 is only charged up to V.sub.DD -Vthn (where Vthn denotes a threshold voltage of the n-type MOSFET).
Thus, if the circuit of FIG. 6 does not have transistors Tr5, Tr8 and Tr9, a transistor Tr6 is not completely turned OFF, thereby causing a DC current between the transistor Tr6 and a transistor Tr7.
Conventionally, in order to solve this problem, the n-type MOSFET transistors Tr5, Tr8 and Tr9 are provided as auxiliary circuits, as illustrated in FIG. 6.
In this configuration with the auxiliary circuits, as illustrated in FIG. 6, when the node N#1 is initially (i.e.) before the signal C bar (at the high level) is inverted from input signal C and transmitted thereto) set to a low level (equal to GND, or ground level), the transistors Tr6 and Tr8 are ON. When the signal C bar is transmitted therethrough, the transistors Tr7 and Tr9 are then turned ON, a node N#2 is at a low level, and the transistor Tr5 is turned ON. Thus, the node N#1 is charged from V.sub.DD -Vthn to V.sub.DD.
When the signal to be transmitted is at the low level, and the node N#1 is initially at the high level, a DC current is generated from the transistor Tr5 toward the signal to be transmitted, and the transistor Tr8 is turned ON by the potential at the node N#1, thereby bringing the node N#2 to the high level. The DC current keeps flowing until the transistor Tr5 is turned OFF. Thus, as the potential at the node N#1 changes from the high level to the low level, the transistor Tr5 and the signal source (low level) collide with each other, thereby generating a DC current flowing from Tr5.fwdarw.Tr4.fwdarw.Tr2.fwdarw.C bar (which is equal to a low level).
As described above, when only the n-type MOSFET is used for the pass gate, due to the characteristics of the n-type transistor, only the signal amplitude "V.sub.DD -Vthn" of a high level signal is transmitted therethrough.
When only the p-type characteristics MOSFET is used for the pass gate, due to the characteristics of the p-type transistor, only the signal amplitude "GND+.linevert split.Vthp.linevert split." of a low level signal is transmitted therethrough (where Vthp denotes the threshold voltage of the p-type MOSFET).
In order to solve these problems, conventionally, the above-described auxiliary circuits are additionally provided. In such a configuration, however, a temporary or steady DC current occurs in the auxiliary circuits.
This results from the formation of the pass gate using only an n-type MOSFET or a p-type MOSFET.